FIG. 1 illustrates a model 10 of a prior art circuit. The modeled circuit includes a capacitive load (such as a membrane) that is connected to a capacitor (which may also be another membrane (or another capacitive load)), using a charge reuse mechanism.
The model 10 includes first resistor R1 11, first capacitor C1 12, first switch 13, input 14 from charge pump, second resistor R2 19, second capacitor C2 18, second switch 17, inductor L 16 and inductor parasitic resistor 15.
Inductor L 16 and inductor parasitic resistor 15 are serially connected to each other.
First resistor R1 11 and first capacitor C1 12 are serially connected between the ground and an input port of first switch 13.
Second resistor R2 19, second capacitor C2 18 are serially connected between the ground and an input port of second switch 17.
First switch 13 may connect R1 11 and C1 12 to the input 14, to inductor L 16 and inductor parasitic resistor 15 or maintain R1 11 and C1 12 disconnected.
Second switch 17 may connect R2 19 and C2 18 to the input 14, to inductor L 16 and inductor parasitic resistor 15 or maintain R2 19 and C2 18 disconnected.
The charge-reuse mechanism allows reusing the capacitive load electric charge. Assume the capacitive load is the second capacitor C2 18 with initially 0 v, and C1 of equal capacitance contains initial charge Q with voltage level of 100 v. Also assume that capacitive load capacitance is 50 pF and that the required capacitive load frequency is 500 KHz. A simple calculation shows that charging the capacitive load from 0 v to 100 v from a power source and discharging from 100 v to ground and vice versa would consume average power of at least 125 mW from the power source (this calculation is based on the capacitor potential energy E=V2C/2). The prior art circuit suggests that capacitive load charging is done by just turning-on the appropriate switch and letting the charge Q flow from C1 to the capacitive load C2 through inductance L. It can be shown that in the ideal case of 0 pure resistance and initial condition of 0 v on C2 all the charge Q will move from C1 to C2 and then the inductance current will change direction. If the switch is then turned off and then turned on again after 1 uS and so on, the 0 v/100 v square wave of 500 KHz will appear on the capacitive load—theoretically without consuming power from the power source. Anyway, since there is parasitic resistance in the circuit (as shown in FIG. 1), the inductor current will change direction too early (i.e. before full charge exchange occurs), which will require refreshment of both capacitors to initial charge condition after every capacitive load cycle (or half-cycle). This is done by discharging the source capacitor to 0 v and adding more charge to the destination capacitor to reach full initial voltage (100 v). This compensation consumes power from the power source, but this time the average power can be much lower than the 125 mW that would be consumed without the charge-reuse mechanism. Actually the power consumption from power source when charge-reuse is used is limited to only cover the power dissipation by the parasitic resistors and capacitive load motion (e.g. if C2 represents a MEMS membrane there is electric power lose due to small dynamic changes of capacitive load capacitance as a result of membrane displacement).
When coming to implement the charge-reuse schematic of FIG. 1 another issue is raised: How to initialize the voltages of the two capacitors after every cycle. Discharging the residual charge to 0 v in one capacitor is easy, but the main problem is to set the high voltage on the other capacitor (e.g. from 98 v to 100 v). If the power source is of a low-voltage it requires some means of charge pump.
There is a need to provide a low-cost power-efficient charge pump mechanism that enables the design of a highly efficient charge-reuse actuator in MEMS devices.